Submicron FET Simulation and Optimisation

In the first part of the project, we were required to investigate the impact of short channel effects on MOSFET performance by simulating a MOSFET with 150nm gate length in Sentaurus. Subsequently, we optimised its performance through a combination of techniques like thinning the oxide layer, increasing the substrate doping and reducing the junction depth.

In the second part of the project, we used Sentaurus Device Editor to implement a GAA FET (Gate-all-around field effect transistor) and then wrote a paper to investigate how cross-sectional geometry can affect its performance. We used DC performance characteristics like sub-threshold swing, drain-induced barrier lowering, output conductance, on-off current ratio to judge the FET’s performance.